Characterizing Parallel Multipliers for Detecting Hardware Trojans.

This paper presents a new analysis method for estimating the detectability of a hardware trojan (HT) that causes a path delay fault (PDF) to parallel multipliers. The proposed method characterizes a parallel multiplier with the average delay of all paths in a multiplier. We show that the average delay, which is determined by its multiplier structure, has a relation to the HT detectabil- ity. The validity of our method is evaluated by an experiment using Monte Carlo tests that measure the detection probabilities of HTs inserted into typi- cal multipliers, and multiple regression analysis. In addition, we demonstrate how the amounts of inserted delay have impacts on the HT detectability. The result shows that, given an inserted delay amount and a multiplier structure, our analysis is useful for estimating the detectability.

Authors

• Akira Ito
• Rei Ueno
• Naofumi Homma
• Takafumi Aoki

Keywords

• Hardware trojans
• Arithmetic algorithms
• Multipliers
• Path delay faults