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Tetsuya Higuchi

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6 papers
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6

AAAI Conference 1999 Conference Paper

An Evolvable Hardware Chip and Its Application as a Multi-Function Prosthetic Hand Controller

  • Isamu Kajitani
  • Tsutomu Hoshino
  • University of Tsukuba; Nobuki Kajihara
  • Adaptive Devices NEC Laboratory
  • RWCP; Masaya Iwata
  • Tetsuya Higuchi
  • Electrotechnical Laboratory

Thispaperdescribesthe applicationof geneticalgorithmsto the biomedicalengineering problem of a multi-function myoelectricprosthetic hand controller. This is achievedby an innovativeLSI chip (EHW chip), i. e. , a VLSIimplementation of Evolvable Hardware(EHW), whichcan adapt its owncircuit structure to its environment autonomouslyand quickly by using genetic algorithms. Usually, a long training period (almost onemonth)is required beforemulti-functionmyoelectric prosthetic handscan be controlled, however, the EHW chip controller developed here can reducethis period andit has beendesignedfor easy implementationwithin a prosthetic hand. Thereare plans to commercialize the prosthetic hand with the EHW chip, and the medical departmentof Hokkaido Universityhas already decidedto adoptthis for clinical treatment.

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IJCAI Conference 1997 Conference Paper

Evolvable Hardware for Generalized Neural Networks

  • Masahiro Murakawa
  • Shuji Yoshizawa
  • Isamu Kajitani
  • Tetsuya Higuchi

This paper describes an evolvable hardware (EHW) system for generalized neural network learning. We have developed an ASIC VLSI chip, which is a building block to configure a scalable neural network hardware system. In our system, both the topology and the hidden layer node functions of a neural network mapped on the chips are dynamically changed using a genetic algorithm. Thus, the most desirable network topology and choice of node function (e. g. Gaussian or sigmoid) for a given application can be determined adaptively. This approach is particularly suited to applications requiring ability to cope with time-varying problems and real-time timing constraints. The chip consists of 15 Digital Signal Processors (DSPs), whose functions and interconnections are reconfigured dynamically according to the chromosomes of the genetic algorithm. Incorporation of local learning hardware increases the learning speed significantly. Simulation results on adaptive equalization in digital mobile communication are also given. Our system is two orders of magnitude faster than a Sun SS20 on the corresponding problem.

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IJCAI Conference 1993 Conference Paper

Evolutionary Learning Strategy using Bug-Based Search

  • Hitoshi Iba
  • Tetsuya Higuchi
  • Hugo deGaris
  • Taisuke Sato

We introduce a new approach to GA (Genetic Algorithms) based problem solving. Earlier GAs did not contain local search (i. e. hill climbing) mechanisms, which led to optimization difficulties, especially in higher dimensions. To overcome such difficulties, we introduce a "bug-based" search strategy, and implement a system called BUGS2. The ideas behind this new approach are derived from biologically realistic bug behaviors. These ideas were confirmed empirically by applying them to some optimization and computer vision problems.

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AAAI Conference 1991 Conference Paper

IXM2: A Parallel Associative Processor for Knowledge Processing

  • Tetsuya Higuchi
  • Tatsumi Furuya
  • Akio Kokubu

This paper describes a parallel associative processor, IXM2, developed mainly for semantic network processing. IXM2 consists of 64 associative processors and 9 network processors, having a total of 256K words of associative memory. The large associative memory enables 65, 536 semantic network nodes to be processed in parallel and reduces the order of algorithmic complexity to O(1) in basic semantic net operations. We claim that intensive use of associative memory provides far superior performance in carrying out the basic operations necessary for semantic network processing: intersection, marker-propagation, and arithmetic operations.

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