Author name cluster

Hans Graf

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8 papers

1 author row

NeurIPS Conference 2008 Conference Paper

A Massively Parallel Digital Learning Processor

Hans Graf
Srihari Cadambi
Venkata Jakkula
Murugan Sankaradass
Eric Cosatto
Srimat Chakradhar
Igor Dourdanovic

We present a new, massively parallel architecture for accelerating machine learning algorithms, based on arrays of variable-resolution arithmetic vector processing elements (VPE). Groups of VPEs operate in SIMD (single instruction multiple data) mode, and each group is connected to an independent memory bank. In this way memory bandwidth scales with the number of VPE, and the main data flows are local, keeping power dissipation low. With 256 VPEs, implemented on two FPGA (field programmable gate array) chips, we obtain a sustained speed of 19 GMACS (billion multiply-accumulate per sec. ) for SVM training, and 86 GMACS for SVM classification. This performance is more than an order of magnitude higher than that of any FPGA implementation reported so far. The speed on one FPGA is similar to the fastest speeds published on a Graphics Processor for the MNIST problem, despite a clock rate of the FPGA that is six times lower. High performance at low clock rates makes this massively parallel architecture particularly attractive for embedded applications, where low power dissipation is critical. Tests with Convolutional Neural Networks and other learning algorithms are under way now.

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NeurIPS Conference 2004 Conference Paper

Parallel Support Vector Machines: The Cascade SVM

Hans Graf
Eric Cosatto
Léon Bottou
Igor Dourdanovic
Vladimir Vapnik

We describe an algorithm for support vector machines (SVM) that can be parallelized efficiently and scales to very large problems with hundreds of thousands of training vectors. Instead of analyzing the whole training set in one optimization step, the data are split into subsets and optimized separately with multiple SVMs. The partial results are combined and filtered again in a ‘Cascade’ of SVMs, until the global optimum is reached. The Cascade SVM can be spread over multiple processors with minimal communication overhead and requires far less memory, since the kernel matrices are much smaller than for a regular SVM. Convergence to the global optimum is guaranteed with multiple passes through the Cascade, but already a single pass provides good generalization. A single pass is 5x – 10x faster than a regular SVM for problems of 100, 000 vectors when implemented on a single processor. Parallel implementations on a cluster of 16 processors were tested with over 1 million vectors (2-class problems), converging in a day or two, while a regular SVM never converged in over a week.

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NeurIPS Conference 1993 Conference Paper

Address Block Location with a Neural Net System

Hans Graf
Eric Cosatto

We developed a system for finding address blocks on mail pieces that can process four images per second. Besides locating the address block, our system also determines the writing style, handwritten or machine printed, and moreover, it measures the skew angle of the text lines and cleans noisy images. A layout analysis of all the elements present in the image is performed in order to distinguish drawings and dirt from text and to separate text of advertisement from that of the destination address. A speed of more than four images per second is obtained on a modular hardware platform, containing a board with two of the NET32K neural net chips, a SP ARC2 processor board, and a board with 2 digital signal processors. The system has been tested with more than 100, 000 images. Its performance depends on the quality of the images, and lies between 85% correct location in very noisy images to over 98% in cleaner images.

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NeurIPS Conference 1993 Conference Paper

Backpropagation without Multiplication

Patrice Simard
Hans Graf

The back propagation algorithm has been modified to work with(cid: 173) out any multiplications and to tolerate comput. ations with a low resolution, which makes it. more attractive for a hardware imple(cid: 173) mentatioll. Numbers are represented in float. ing point format with 1 bit mantissa and 3 bits in the exponent for the states, and 1 bit mantissa and 5 bit exponent. for the gradients, while the weights are 16 bit fixed-point numbers. In this way, all the computations can be executed with shift and add operations. Large nehvorks with over 100, 000 weights were t. rained and demonstrat. ed the same per(cid: 173) formance as networks comput. ed with full precision. An estimate of a circuit implementatioll shows that a large network can be placed on a single chip, reaching more t. han 1 billion weight updat. es pel' second. A speedup is also obtained on any machine where a mul(cid: 173) tiplication is slower than a shift operat. ioJl.

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NeurIPS Conference 1991 Conference Paper

Image Segmentation with Networks of Variable Scales

Hans Graf
Craig Nohl
Jan Ben

We developed a neural net architecture for segmenting complex images, i. e. , to localize two-dimensional geometrical shapes in a scene, without prior knowledge of the objects' positions and sizes. A scale variation is built into the network to deal with varying sizes. This algo(cid: 173) rithm has been applied to video images of railroad cars, to find their identification numbers. Over 95% of the characlers were located correctly in a data base of 300 images, despile a large variation in light(cid: 173) ing conditions and often a poor quality of the characters. A part of the network is executed on a processor board containing an analog neural net chip (Graf et aI. 1991). while the rest is implemented as a software model on a workstation or a digital signal processor.

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NeurIPS Conference 1989 Conference Paper

A Reconfigurable Analog VLSI Neural Network Chip

Srinagesh Satyanarayana
Yannis Tsividis
Hans Graf

1024 distributed-neuron synapses have been integrated in an active area of 6. 1mm x 3. 3mm using a 0. 9p. m, double-metal, single-poly, n-well CMOS technology. The distributed-neuron synapses are ar(cid: 173) ranged in blocks of 16, which we call '4 x 4 tiles'. Switch matrices are interleaved between each of these tiles to provide programma(cid: 173) bility of interconnections. With a small area overhead (15 %), the 1024 units of the network can be rearranged in various configura(cid: 173) tions. Some of the possible configurations are, a 12-32-12 network, a 16-12-12-16 network, two 12-32 networks etc. (the numbers sep(cid: 173) arated by dashes indicate the number of units per layer, including the input layer). Weights are stored in analog form on MaS ca(cid: 173) pacitors. The synaptic weights are usable to a resolution of 1 % of their full scale value. The limitation arises due to charge injection from the access switch and charge leakage. Other parameters like gain and shape of nonlinearity are also programmable.

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NeurIPS Conference 1988 Conference Paper

This paper describes the construction of a system that recognizes hand-printed digits, using a combination of classical techniques and neural-net methods. The system has been trained and tested on real-world data, derived from zip codes seen on actual U. S. Mail. The system rejects a small percentage of the examples as unclassifiable, and achieves a very low error rate on the remaining examples. The system compares favorably with other state-of-the art recognizers. While some of the methods are specific to this task, it is hoped that many of the techniques will be applicable to a wide range of recognition tasks.

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NeurIPS Conference 1987 Conference Paper

Microelectronic Implementations of Connectionist Neural Networks

Stuart Mackie
Hans Graf
Daniel Schwartz
John Denker

In this paper we discuss why special purpose chips are needed for useful implementations of connectionist neural networks in such applications as pattern recognition and classification. Three chip designs are described: a hybrid digital/analog programmable connection matrix, an analog connection matrix with adjustable connection strengths, and a digital pipe lined best-match chip. The common feature of the designs is the distribution of arithmetic processing power amongst the data storage to minimize data movement.

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